Verilog Module

A Verilog module is a self-contained unit that defines a specific functionality. It serves as a blueprint for creating instances of that functionality in your design. Modules encapsulate a set of logic, inputs, outputs, and potentially internal signals.

Verilog Port

Ports are the communication interfaces of a Verilog module. They define how information flows in and out of the module. Ports can be inputs, outputs, or bidirectional.

Verilog Module Instantiations

Module instantiations are instances of a module created within another module. They allow you to use the functionality defined in one module within another.

Verilog Assign Statements

The assign statement connects a source to a destination, creating a continuous assignment. It's used to connect wires or signals directly without using a procedural block.

Verilog Always Block

The always block defines procedural logic that executes whenever the conditions specified within it are met. It's often used for sequential logic and state machines.

In the above always block the logic statements will be executed at each positive edge of the clock signal.

Verilog Initial Block

The initial block contains procedural code that's executed only once at the start of simulation. It's used for setting initial values or performing setup tasks.

These building blocks collectively allow you to create complex digital designs by defining the structure, behavior, and interactions of different components in your Verilog code.