The conditional statements are used to determine whether particular statement should be executed or not. Control statements in Verilog is similar to control statements in C.

if-else

If the expression in if condition is true then the statements inside the if condition will be executed or if it is false the statements inside the else condition will be executed.

Syntax:

if (expression)
    [statement]
else
    [statement]

if-else for multiple statements should be

if (expression) begin
    [multiple statements]
end

else begin
  [multiple statements]
end

Example:

Similar to C, it is possible to have nested if statements in Verilog.

Conditional Operator

You can assign a value based on a condition by using the conditional operator.

Syntax:

variable = <condition> ? <expression1> : <expression2>

If the condition is true expression1 is assigned to the variable or else expression2 is assigned to the variable.