Problem Statement: Design and simulate behavioral model of a FIFO.

What is FIFO?

FIFO is similar to a supermarket checkout line, where the first person in line is served first.

Implementing a behavioral model of FIFO

• Some important points to note
  • Two input signals push and pop are used to insert and delete data from the data structure. While asserting push, we must also provide some data to insert in the FIFO.
  • Two pointers, Rptr (for read) and Wptr (for write) will be used to maintain the FIFO. Rptr is incremented upon a read, and the Wptr is incremented upon a write.
  • Two flags, full and empty can be used to check and display the status of the FIFO.
    • While full = 1, no data shall be inserted in the FIFO, even if provided with the push signal.
    • Similarly, while empty = 1, no data shall be deleted and/or output should not change, even if pop signal tries to delete.

1. Create a new Verilog file named fifo.v, and copy-paste the below design.

2. Create a new Verilog file and type the below testbench code provided below. Save the file with the same name as the module name.

3. Compile the code and check for any syntax errors using the below command.

   iverilog fifo.v tb_fifo.v -o fifo
   

4. If there are no errors, use the below command for running the simulation.

   vvp fifo
   

   You will see the values of signals being monitored across each clocktick.

5. If all looks well, use the below command for viewing the waveform. Add the signals from tb_fifo design to the window to view the simulation output as shown in below image.

   gtkwave fifo.vcd
   

   
   
   
   • At time, t = 100 ns, push = 1 and in = 32'h00000008, the data is being saved in the FIFO and thus it is neither full nor empty.
   • Eventually when the pop = 1, the data stored in FIFO is available at the out port, one at a time.
   • And as soon as the last data is popped out, the FIFO becomes empty, thus empty = 1.