Up Down Counter
Problem Statement: Design and simulate a four-bit Up Down Counter.
What is Counter?
The counter has a defined width
N
, which means that it can count maximum up to 2N-1
and then rolls back to 0
.
Here, we will design a 4-bit Up Down counter. Based on a control signal named up_down
, the counter will either count up
or down
from the current state of the counter.
Implementing a 4-bit up down counter
-
Create a new Verilog file named
up_down_counter.v
, and copy-paste the below design of 4-bit up down counter. -
Create a new Verilog file and type the below testbench code provided below. Save the file with the same name as the module name.
-
Compile the code and check for any syntax errors using the below command.
iverilog up_down_counter.v tb_up_down_counter.v -o up_down_counter
-
If there are no errors, use the below command for running the simulation.
vvp up_down_counter
You will see the values of signals being monitored across each clocktick.
-
If all looks well, use the below command for viewing the waveform. Add the signals from
tb_up_down_counter
design to the window to view the simulation output as shown in below image.gtkwave up_down_counter.vcd